The present invention relates to a wiring method involving on-chip modification for an LSI and more particularly to a method for changing the logic of a semiconductor integrated circuit chip by cutting or connecting a wire pattern provided on the chip after manufacturing the chip and to a method which can offer more freedom of modifying portions and changing logic.
Today, as a semiconductor integrated circuit becomes more integrated and minute, more complicated and massive logical information is required which indicates logical connection consisting of circuit element groups composing an LSI and signal lines connecting these circuit element groups.
Even if some logical failure occurs in an LSI, therefore, it has been difficult to find all of the logical failures in the design stage. Furthermore, in the manufacturing stage, some failure may occur. This kind of logical failure cannot be found until the LSI is mounted to a device and is checked. In such a case, re-manufacturing of the LSI is preferable, but it requires such a long period of delay in the development of a device having the LSI mounted thereon, which delay is not preferable.
In order to cope with a case wherein some logical failure is found on a LSI mounted on a device, various kinds of techniques have been studied and proposed for working wiring, repairing defective portions and changing the LSI logic for a short time by cutting or connecting one or more wires provided on the LSI chip.
According to a first prior art technique, as disclosed in JP-A-62-229956, a method is provided for connecting or cutting the wiring of an LSI by an energy beam such as a ion beam or an laser induced CVD process.
According to a second prior art technique, as disclosed in JP-A-62-298134, preliminary wiring is provided within the LSI for facilitating connections in the LSI wiring.
According to a third prior art technique, as disclosed in JP-A-2-15657, an interval between two wires in the LSI wiring is kept so that the interval is used for connecting or cutting the wire.
For defining a spot on which a wire is to be cut and/or connected, the foregoing prior art disadvantageously has to consider the state of a wire above or adjacent to the spot interest. If the adjacent condition is not met, therefore, it is impossible to connect or cut the wire provided in the LSI, thereby inhibiting the ability to change the LSI logic by repairing.
Further, the foregoing prior art disadvantageously has to extend a wire pattern interval or pull out the wire pattern to the top wiring layer for the purpose of facilitating connecting or cutting on the initial design of an LSI to be repaired.